In a typical computing system, when processing devices are in communication across a bus with differential signals, problems may arise due to noise on the bus. If a particular processing device is in a sleep mode or commonly referred to as an idle mode, or otherwise not expecting an incoming signal, the noise on the bus may be misinterpreted, thereby causing unnecessary computations in a processing device. This not only potentially reduces battery life by increased power consumption for improper and unwarranted computations, but can also cause the processing device to improperly attempt to interpret the noise as an incoming data signal. Currently, there exist techniques to separate differential noise level from differential signal levels to determine if the incoming signal is a valid differential signal. A common approach is to provide functionality using 4 differential stages with sequential logic to differentiate noise from signal information.
More specifically, 4 differential stages may utilize 2 differential voltage comparators with the window, using a well known schematic, to compare differential signal levels provided across a bus with reference to two reference voltages. These two differential comparators with the window can identify whether incoming differential signal level is higher than high noise level and lower than low noise level. In this approach, a logical device is needed to determine if an input signal is higher than a first reference voltage or lower than a second reference voltage. These 4 differential stages (two differential comparators with window) not only require significant amount of the chip area, but also require large amounts of power consumption.
Therefore, there exists a need for a new solution that allows for the determination of an incoming differential signal either to be processed as an incoming data signal or be ignored as noise, wherein the incoming signal detection device consumes small chip area and also reduces the amount of chip power consumption.